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SLOC Program for VHDL/Verilog
Hey Guys. I've been tasked to come up w/ a Source lines of code (SLOC) program to count the number of lines for Verilog and VHDL. I need to count the physicial lines of code, logical lines of code, and also the number of commented lines.
Anyone have any ideas on an algorithm I can use for this? |
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